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Refinado por: Nome da Publicação: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems remover
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11
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques
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A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques

Wei, Jiahao ; Wang, Haihua ; Zhao, Tian ; Jiang, Yu-Long ; Wan, Jing

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1250-1254 [Periódico revisado por pares]

New York: IEEE

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12
Defect-Oriented Test: Effectiveness in High Volume Manufacturing
Defect-Oriented Test: Effectiveness in High Volume Manufacturing
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Defect-Oriented Test: Effectiveness in High Volume Manufacturing

Hapke, Friedrich ; Howell, Will ; Maxwell, Peter ; Brazil, Edward ; Venkataraman, Srikanth ; Dutta, Rudrajit ; Glowatz, Andreas ; Fast, Anja ; Rajski, Janusz

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-03, Vol.40 (3), p.584-597 [Periódico revisado por pares]

IEEE

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13
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation
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GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation

Alrahis, Lilas ; Knechtel, Johann ; Klemme, Florian ; Amrouch, Hussam ; Sinanoglu, Ozgur

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1 [Periódico revisado por pares]

New York: IEEE

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14
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From −200 °C to +300 °C)
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From −200 °C to +300 °C)
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SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From −200 °C to +300 °C)

Petrosyants, Konstantin O. ; Sambursky, Lev M. ; Kozhukhov, Maxim V. ; Ismail-Zade, Mamed R. ; Kharitonov, Igor A. ; Li, Bo

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-04, Vol.40 (4), p.708-722 [Periódico revisado por pares]

New York: IEEE

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15
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review
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Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Azam, Sadia ; Dall'Ora, Nicola ; Fraccaroli, Enrico ; Gillon, Renaud ; Fummi, Franco

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-01, Vol.43 (1), p.1-1 [Periódico revisado por pares]

IEEE

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16
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
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Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits

Rai, Shubham ; Calvino, Alessandro Tempia ; Riener, Heinz ; De Micheli, Giovanni ; Kumar, Akash

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-03, Vol.42 (3), p.914-927 [Periódico revisado por pares]

New York: IEEE

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17
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits
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On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Burchard, Jan ; Erb, Dominik ; Reddy, Sudhakar M. ; Singh, Adit D. ; Becker, Bernd

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-10, Vol.37 (10), p.2152-2165 [Periódico revisado por pares]

New York: IEEE

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18
An Automatic Circuit Design Framework for Level Shifter Circuits
An Automatic Circuit Design Framework for Level Shifter Circuits
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An Automatic Circuit Design Framework for Level Shifter Circuits

Hong, Jiwoo ; Kim, Sunghoon ; Jeon, Dongsuk

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5169-5181 [Periódico revisado por pares]

New York: IEEE

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19
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture
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Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture

Zhang, Xiaoyu ; Liu, Rui ; Song, Tao ; Yang, Yuxin ; Han, Yinhe ; Chen, Xiaoming

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.5071-5084 [Periódico revisado por pares]

New York: IEEE

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20
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model
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Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model

Rajasekharan, Dinesh ; Gaidhane, Amol ; Trivedi, Amit Ranjan ; Chauhan, Yogesh Singh

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.2107-2114 [Periódico revisado por pares]

New York: IEEE

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