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A Novel Table-Based Approach for Design of FinFET Circuits
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A Novel Table-Based Approach for Design of FinFET Circuits

Thakker, R.A. ; Sathe, C. ; Sachid, A.B. ; Shojaei Baghini, M. ; Ramgopal Rao, V. ; Patil, M.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-07, Vol.28 (7), p.1061-1070 [Periódico revisado por pares]

New York: IEEE

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A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance
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A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance

Thakker, R.A. ; Sathe, C. ; Baghini, M.S. ; Patil, M.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.627-631 [Periódico revisado por pares]

New York: IEEE

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3
An efficient algorithm for finding multiple DC solutions based on the SPICE-oriented Newton homotopy method
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An efficient algorithm for finding multiple DC solutions based on the SPICE-oriented Newton homotopy method

Ushida, A. ; Yamagami, Y. ; Nishio, Y. ; Kinouchi, I. ; Inoue, Y.

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-03, Vol.21 (3), p.337-348 [Periódico revisado por pares]

New York: IEEE

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4
ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism
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ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism

Rouying Zhan ; Haigang Feng ; Qiong Wu ; Haolu Xie ; Xiaokang Guan ; Guang Chen ; Wang, A.Z.H.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-10, Vol.23 (10), p.1421-1428 [Periódico revisado por pares]

New York: IEEE

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5
A framework for testing special-purpose memories
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A framework for testing special-purpose memories

Sidorowicz, P.R. ; Brzozowski, J.A.

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-12, Vol.21 (12), p.1459-1468 [Periódico revisado por pares]

New York: IEEE

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6
Highly accurate and simple models for CML and ECL gates
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Artigo
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Highly accurate and simple models for CML and ECL gates

Alioto, M. ; Palumbo, G.

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-09, Vol.18 (9), p.1369-1375 [Periódico revisado por pares]

New York, NY: IEEE

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7
Modeling of avalanche generation current of bipolar junction transistors for computer circuit simulation
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Modeling of avalanche generation current of bipolar junction transistors for computer circuit simulation

Divekar, D.A. ; Lovelace, R.E.

IEEE transactions on computer-aided design of integrated circuits and systems, 1982-07, Vol.1 (3), p.112-116 [Periódico revisado por pares]

IEEE

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8
Practical Integration of Process, Device, and Circuit Simulation
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Practical Integration of Process, Device, and Circuit Simulation

Sokel, R.I. ; MacMillen, D.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 1985-10, Vol.4 (4), p.554-560 [Periódico revisado por pares]

IEEE

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9
Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors
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Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

Fu, Mingye ; Jiang, Nianhua ; Bornemann, Jens ; Feng, Quanyuan

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.16-26 [Periódico revisado por pares]

New York: IEEE

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10
Germanium-and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis
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Germanium-and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis

Sugiura, Takaya ; Yamakiri, Shiun ; Nakano, Nobuhiko

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-10, Vol.42 (10), p.1-1 [Periódico revisado por pares]

New York: IEEE

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