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A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
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A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Park, Hangi ; Hwang, Chanwoong ; Seong, Taeho ; Choi, Jaehyouk

IEEE journal of solid-state circuits, 2022-12, Vol.57 (12), p.3527-3537 [Periódico revisado por pares]

New York: IEEE

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2
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
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A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

Park, Suneui ; Yoo, Seyeon ; Shin, Yuhwan ; Lee, Jeonghyun ; Choi, Jaehyouk

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-12 [Periódico revisado por pares]

New York: IEEE

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3
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
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A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier

Jo, Yongwoo ; Kim, Juyeop ; Shin, Yuhwan ; Park, Hangi ; Hwang, Chanwoong ; Lim, Younghyun ; Choi, Jaehyouk

IEEE journal of solid-state circuits, 2023-12, Vol.58 (12), p.3338-3350 [Periódico revisado por pares]

New York: IEEE

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4
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
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A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator

Yoo, Seyeon ; Choi, Seojin ; Lee, Yongsun ; Seong, Taeho ; Lim, Younghyun ; Choi, Jaehyouk

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.298-309 [Periódico revisado por pares]

New York: IEEE

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5
A Fractional- N Synthesizer Based on Programmable Frequency Multiplier for 5G ^ Communication System
A Fractional- N Synthesizer Based on Programmable Frequency Multiplier for 5G ^ Communication System
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A Fractional- N Synthesizer Based on Programmable Frequency Multiplier for 5G ^ Communication System

Hong, Nam-Pyo ; Nam, Kyu-Hyun ; Park, Jun-Seok

IEEE transactions on microwave theory and techniques, 2023-04, Vol.71 (4), p.1-18 [Periódico revisado por pares]

New York: IEEE

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6
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
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Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Elkholy, Ahmed ; Talegaonkar, Mrunmay ; Anand, Tejasvi ; Kumar Hanumolu, Pavan

IEEE journal of solid-state circuits, 2015-12, Vol.50 (12), p.3160-3174 [Periódico revisado por pares]

New York: IEEE

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7
A 12.8-15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
A 12.8-15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
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A 12.8-15.0-GHz Low-Jitter Fractional- N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation

Kim, Juyeop ; Jo, Yongwoo ; Park, Hangi ; Seong, Taeho ; Lim, Younghyun ; Choi, Jaehyouk

IEEE journal of solid-state circuits, 2024-02, Vol.59 (2), p.1-11 [Periódico revisado por pares]

New York: IEEE

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8
Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements
Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements
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Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements

Ali, Zeeshan ; Elsayed, Mostafa ; Tiwari, Girish ; Ahmad, Meraj ; Kernec, Julien Le ; Heidari, Hadi ; Gupta, Shalabh

IEEE transactions on instrumentation and measurement, 2024-01, Vol.73, p.1-1 [Periódico revisado por pares]

New York: IEEE

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9
22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time-to-digital converter in CMOS 65 nm for single photon avalanche diode array
22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time-to-digital converter in CMOS 65 nm for single photon avalanche diode array
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22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time-to-digital converter in CMOS 65 nm for single photon avalanche diode array

Nolet, F ; Roy, N ; Carrier, S ; Bouchard, J ; Fontaine, R ; Charlebois, S.A ; Pratte, J.-F

Electronics letters, 2020-04, Vol.56 (9), p.424-426 [Periódico revisado por pares]

The Institution of Engineering and Technology

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10
Study of Subharmonically Injection-Locked PLLs
Study of Subharmonically Injection-Locked PLLs
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Study of Subharmonically Injection-Locked PLLs

Lee, Jri ; Wang, Huaide

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1539-1553 [Periódico revisado por pares]

New York, NY: IEEE

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