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0.0012 mm super( 2), 8 mW, single-to-differential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate

Chen, Yong ; Mak, Pui-In ; Zhang, Li ; Qian, He ; Wang, Yan

Electronics letters, 2013-05, Vol.49 (11), p.1-1 [Periódico revisado por pares]

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Título:
0.0012 mm super( 2), 8 mW, single-to-differential converter with < 1.1% data cross error and < 3.4 ps RMS jitter up to 14 Gbit/s data rate
Autor: Chen, Yong ; Mak, Pui-In ; Zhang, Li ; Qian, He ; Wang, Yan
Assuntos: Balancing ; CMOS ; Consumption ; Converters ; Error analysis ; Errors ; High speed ; Jitter
É parte de: Electronics letters, 2013-05, Vol.49 (11), p.1-1
Notas: ObjectType-Article-1
SourceType-Scholarly Journals-1
content type line 23
ObjectType-Feature-2
Descrição: An extremely compact, doubly balancing single-to-differential converter (S2D) for high-speed wireline systems is reported. It incorporates a two-stage topology with 'coarse balancing' in the first stage and 'fine balancing' in the second stage by adopting a compact 'positive-feedback active inductor' that simultaneously boosts the signal bandwidth. Fabricated in 65 nm CMOS, the S2D measures < 1.1% data cross error and < 3.4 ps RMS jitter up to a 14 Gbit/s data rate. The die occupies 0.0012 mm super( 2) and consumes 8 mW.
Idioma: Inglês

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