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1-D Cell Generation With Printability Enhancement
1-D Cell Generation With Printability Enhancement
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1-D Cell Generation With Printability Enhancement

Po-Hsun Wu ; Lin, M. P. ; Tung-Chieh Chen ; Tsung-Yi Ho ; Yu-Chuan Chen ; Shun-Ren Siao ; Shu-Hung Lin

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-03, Vol.32 (3), p.419-432 [Periódico revisado por pares]

New York: IEEE

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2
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion
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3-D numerical modeling of thermal flow for insulating thin film using surface diffusion

Fujinaga, M. ; Tottori, I. ; Kunikiyo, T. ; Uchida, T. ; Kotani, N. ; Tsukamoto, K.

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-05, Vol.14 (5), p.631-638 [Periódico revisado por pares]

New York, NY: IEEE

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3
Accurate Multi-segment Probability Density Estimation Through Moment Matching
Accurate Multi-segment Probability Density Estimation Through Moment Matching
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Accurate Multi-segment Probability Density Estimation Through Moment Matching

Krishnan, Rahul ; Wu, Wei ; Bodapati, Srinivas ; He, Lei

IEEE transactions on computer-aided design of integrated circuits and systems, 2023, p.1-1 [Periódico revisado por pares]

IEEE

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4
Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors
Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors
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Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

Fu, Mingye ; Jiang, Nianhua ; Bornemann, Jens ; Feng, Quanyuan

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.16-26 [Periódico revisado por pares]

New York: IEEE

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5
Adaptive mesh refinement for multilayer process simulation using the finite element method
Adaptive mesh refinement for multilayer process simulation using the finite element method
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Adaptive mesh refinement for multilayer process simulation using the finite element method

Baccus, B. ; Collard, D. ; Dubois, E.

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-03, Vol.11 (3), p.396-403 [Periódico revisado por pares]

NEW YORK: IEEE

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6
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model
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Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

Jiang Hu ; Sapatnekar, S.S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-04, Vol.19 (4), p.446-458 [Periódico revisado por pares]

New York: IEEE

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7
AMGIE-A synthesis environment for CMOS analog integrated circuits
AMGIE-A synthesis environment for CMOS analog integrated circuits
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AMGIE-A synthesis environment for CMOS analog integrated circuits

Van der Plas, G. ; Debyser, G. ; Leyn, F. ; Lampaert, K. ; Vandenbussche, J. ; Gielen, G.G.E. ; Sansen, W. ; Veselinovic, P. ; Leenarts, D.

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-09, Vol.20 (9), p.1037-1058 [Periódico revisado por pares]

New York: IEEE

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8
An accurate analytical delay model for BiCMOS driver circuits
An accurate analytical delay model for BiCMOS driver circuits
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An accurate analytical delay model for BiCMOS driver circuits

Diaz, C.H. ; Kang, S.-M. ; Leblebici, Y.

IEEE transactions on computer-aided design of integrated circuits and systems, 1991-05, Vol.10 (5), p.577-588 [Periódico revisado por pares]

New York, NY: IEEE

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9
An algorithm for functional verification of digital ECL circuits
An algorithm for functional verification of digital ECL circuits
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An algorithm for functional verification of digital ECL circuits

Brauer, E.J. ; Sung-Mo Kang

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-12, Vol.14 (12), p.1546-1556 [Periódico revisado por pares]

New York, NY: IEEE

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10
Analog and Mixed-Signal IC Security via Sizing Camouflaging
Analog and Mixed-Signal IC Security via Sizing Camouflaging
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Analog and Mixed-Signal IC Security via Sizing Camouflaging

Leonhard, Julian ; Sayed, Alhassan ; Louerat, Marie-Minerve ; Aboushady, Hassan ; Stratigopoulos, Haralampos-G.

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.822-835 [Periódico revisado por pares]

New York: IEEE

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