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A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
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A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm

Keller, Ben ; Venkatesan, Rangharajan ; Dai, Steve ; Tell, Stephen G. ; Zimmer, Brian ; Sakr, Charbel ; Dally, William J. ; Gray, C. Thomas ; Khailany, Brucek

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1-13 [Periódico revisado por pares]

New York: IEEE

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2
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators
HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators
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HPPI: A High-Performance Photonic Interconnect Design for Chiplet-Based DNN Accelerators

Li, Guanglong ; Ye, Yaoyao

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, Vol.43 (3), p.1-1 [Periódico revisado por pares]

New York: IEEE

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3
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
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A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Zimmer, Brian ; Venkatesan, Rangharajan ; Shao, Yakun Sophia ; Clemons, Jason ; Fojtik, Matthew ; Jiang, Nan ; Keller, Ben ; Klinefelter, Alicia ; Pinckney, Nathaniel ; Raina, Priyanka ; Tell, Stephen G. ; Zhang, Yanqing ; Dally, William J. ; Emer, Joel S. ; Gray, C. Thomas ; Keckler, Stephen W. ; Khailany, Brucek

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.920-932 [Periódico revisado por pares]

New York: IEEE

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4
An Energy-Efficient FPGA-Based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolution
An Energy-Efficient FPGA-Based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolution
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An Energy-Efficient FPGA-Based Deconvolutional Neural Networks Accelerator for Single Image Super-Resolution

Chang, Jung-Woo ; Kang, Keon-Woo ; Kang, Suk-Ju

IEEE transactions on circuits and systems for video technology, 2020-01, Vol.30 (1), p.281-295 [Periódico revisado por pares]

New York: IEEE

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5
TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators
TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators
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TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators

Qi, Yangjie ; Zhang, Shuo ; Taha, Tarek M.

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1-1 [Periódico revisado por pares]

New York: IEEE

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6
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead
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Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Capra, Maurizio ; Bussolino, Beatrice ; Marchisio, Alberto ; Masera, Guido ; Martina, Maurizio ; Shafique, Muhammad

IEEE access, 2020, Vol.8, p.225134-225180 [Periódico revisado por pares]

Piscataway: IEEE

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7
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
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T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training

Heo, Jaehoon ; Kim, Junsoo ; Lim, Sukbin ; Han, Wontak ; Kim, Joo-Young

IEEE journal of solid-state circuits, 2023-03, Vol.58 (3), p.600-613 [Periódico revisado por pares]

New York: IEEE

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8
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference
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PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Zhang, Bo ; Yin, Shihui ; Kim, Minkyu ; Saikia, Jyotishman ; Kwon, Soonwan ; Myung, Sungmeen ; Kim, Hyunsoo ; Kim, Sang Joon ; Seo, Jae-Sun ; Seok, Mingoo

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1-14 [Periódico revisado por pares]

New York: IEEE

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9
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High Performance Deep Learning Acceleration
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High Performance Deep Learning Acceleration
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Mortar-FP8: Morphing the Existing FP32 Infrastructure for High Performance Deep Learning Acceleration

Li, Hongyan ; Lu, Hang ; Li, Xiaowei

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, Vol.43 (3), p.1-1 [Periódico revisado por pares]

New York: IEEE

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10
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
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DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

Whatmough, Paul N. ; Lee, Sae Kyu ; Brooks, David ; Wei, Gu-Yeon

IEEE journal of solid-state circuits, 2018-09, Vol.53 (9), p.2722-2731 [Periódico revisado por pares]

New York: IEEE

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