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Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System
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Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System

ITO, Kohei ; IIZUKA, Kensuke ; HIRONAKA, Kazuei ; HU, Yao ; KOIBUCHI, Michihiro ; AMANO, Hideharu

IEICE Transactions on Information and Systems, 2021/12/01, Vol.E104.D(12), pp.2029-2039 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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2
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Matsutani, H. ; Koibuchi, M. ; Amano, H. ; Yoshinaga, T.

IEEE transactions on computers, 2011-06, Vol.60 (6), p.783-799 [Periódico revisado por pares]

New York: IEEE

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3
Prediction router: Yet another low latency on-chip router architecture
Prediction router: Yet another low latency on-chip router architecture
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Prediction router: Yet another low latency on-chip router architecture

Matsutani, H. ; Koibuchi, M. ; Amano, H. ; Yoshinaga, T.

2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009, p.367-378

IEEE

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4
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet
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A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet

Koibuchi, M ; Otsuka, T ; Kudoh, T ; Amano, H

IEEE transactions on parallel and distributed systems, 2011-02, Vol.22 (2), p.217-230 [Periódico revisado por pares]

New York: IEEE

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5
Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 cluster
Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 cluster
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Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 cluster

Koibuchi, M. ; Watanabe, K. ; Otsuka, T. ; Amano, H.

IEEE transactions on parallel and distributed systems, 2005-08, Vol.16 (8), p.747-759 [Periódico revisado por pares]

New York: IEEE

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6
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet
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Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet

Otsuka, T. ; Koibuchi, M. ; Kudoh, T. ; Amano, H.

2006 International Conference on Parallel Processing (ICPP'06), 2006, p.479-486

IEEE

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7
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

Koibuchi, M. ; Matsutani, H. ; Amano, H. ; Mark Pinkston, T.

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008, p.13-22

IEEE

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8
VLAN-based minimal paths in PC cluster with Ethernet on mesh and torus
VLAN-based minimal paths in PC cluster with Ethernet on mesh and torus
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VLAN-based minimal paths in PC cluster with Ethernet on mesh and torus

Otsuka, T. ; Koibuchi, M. ; Jouraku, A. ; Amano, H.

2005 International Conference on Parallel Processing (ICPP'05), 2005, p.567-576

IEEE

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9
Run-time power gating of on-chip routers using look-ahead routing
Run-time power gating of on-chip routers using look-ahead routing
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Run-time power gating of on-chip routers using look-ahead routing

Matsutani, Hiroki ; Koibuchi, Michihiro ; Wang, Daihan ; Amano, Hideharu

2008 Asia and South Pacific Design Automation Conference, 2008, p.55-60

IEEE Computer Society Press

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10
Routing algorithms based on 2D turn model for irregular networks
Routing algorithms based on 2D turn model for irregular networks
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Routing algorithms based on 2D turn model for irregular networks

Jouraku, A. ; Koibuchi, M. ; Amano, H. ; Funahashi, A.

Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02, 2002, p.289-294

IEEE

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