Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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1 |
Material Type: Artigo
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Fat H-Tree: A Cost-Efficient Tree-Based On-Chip NetworkMatsutani, H. ; Koibuchi, M. ; Yamada, Y. ; Hsu, D.F. ; Amano, H.IEEE transactions on parallel and distributed systems, 2009-08, Vol.20 (8), p.1126-1141 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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2 |
Material Type: Artigo
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An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular NetworksJouraku, A. ; Koibuchi, M. ; Amano, H.IEEE transactions on parallel and distributed systems, 2007-03, Vol.18 (3), p.320-333 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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3 |
Material Type: Ata de Congresso
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Layout-conscious random topologies for HPC off-chip interconnectsKoibuchi, M. ; Fujiwara, I. ; Matsutani, H. ; Casanova, H.2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.484-495IEEETexto completo disponível |
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4 |
Material Type: Artigo
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Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 clusterKoibuchi, M. ; Watanabe, K. ; Otsuka, T. ; Amano, H.IEEE transactions on parallel and distributed systems, 2005-08, Vol.16 (8), p.747-759 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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5 |
Material Type: Artigo
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A Survey and Evaluation of Topology-Agnostic Deterministic Routing AlgorithmsFlich, J. ; Skeie, T. ; Mejia, A. ; Lysne, O. ; Lopez, P. ; Robles, A. ; Duato, J. ; Koibuchi, M. ; Rokicki, T. ; Sancho, J. C.IEEE transactions on parallel and distributed systems, 2012-03, Vol.23 (3), p.405-425 [Periódico revisado por pares]IEEETexto completo disponível |
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6 |
Material Type: Ata de Congresso
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A case for random shortcut topologies for HPC interconnectsKoibuchi, M. ; Matsutani, H. ; Amano, H. ; Hsu, D. F. ; Casanova, H.2012 39th Annual International Symposium on Computer Architecture (ISCA), 2012, p.177-188IEEETexto completo disponível |
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7 |
Material Type: Ata de Congresso
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Tightly-Coupled Multi-Layer Topologies for 3-D NoCsMatsutani, H. ; Koibuchi, M. ; Amano, H.2007 International Conference on Parallel Processing (ICPP 2007), 2007, p.75-75IEEESem texto completo |
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8 |
Material Type: Ata de Congresso
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L-turn routing: an adaptive routing in irregular networksKoibuchi, M. ; Funahashi, A. ; Jouraku, A. ; Amano, H.International Conference on Parallel Processing, 2001, 2001, p.383-392IEEETexto completo disponível |
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9 |
Material Type: Ata de Congresso
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Prediction router: Yet another low latency on-chip router architectureMatsutani, H. ; Koibuchi, M. ; Amano, H. ; Yoshinaga, T.2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009, p.367-378IEEETexto completo disponível |
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10 |
Material Type: Artigo
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A Switch-Tagged Routing Methodology for PC Clusters with VLAN EthernetKoibuchi, M ; Otsuka, T ; Kudoh, T ; Amano, HIEEE transactions on parallel and distributed systems, 2011-02, Vol.22 (2), p.217-230 [Periódico revisado por pares]New York: IEEETexto completo disponível |