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Reinforcement Learning for Multi-Agent Systems with Temporal Logic Specifications
Reinforcement Learning for Multi-Agent Systems with Temporal Logic Specifications
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Reinforcement Learning for Multi-Agent Systems with Temporal Logic Specifications

TERASHIMA, Keita ; KOBAYASHI, Koichi ; YAMASHITA, Yuh

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2024/01/01, Vol.E107.A(1), pp.31-37 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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2
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
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ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits

USHIODA, Yuya ; KANEKO, Mineo

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2024/03/01, Vol.E107.A(3), pp.600-609 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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3
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
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A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits

MATSUO, Ryosuke ; SHIOMI, Jun ; ISHIHARA, Tohru ; ONODERA, Hidetoshi ; SHINYA, Akihiko ; NOTOMI, Masaya

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/11/01, Vol.E104.A(11), pp.1546-1554 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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4
SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking
SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking
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SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking

CHEN, Yung-Chih

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2020/05/01, Vol.E103.A(5), pp.733-740 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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5
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits
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Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits

MATSUO, Ryosuke ; SHIOMI, Jun ; ISHIHARA, Tohru ; ONODERA, Hidetoshi ; SHINYA, Akihiko ; NOTOMI, Masaya

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/12/01, Vol.E102.A(12), pp.1751-1759 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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6
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM
An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM
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An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM

IGARASHI, Mitsuhiko ; UCHIDA, Yuuki ; TAKAZAWA, Yoshio ; YABUUCHI, Makoto ; TSUKAMOTO, Yasumasa ; SHIBUTANI, Koji ; KOBAYASHI, Kazutoshi

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2021/11/01, Vol.E104.A(11), pp.1536-1545 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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7
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units
Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units
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Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic Units

ALI, Md Belayet ; HIRAYAMA, Takashi ; YAMANAKA, Katsuhisa ; NISHITANI, Yasuaki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/12/01, Vol.E101.A(12), pp.2231-2243 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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8
Hierarchical Control of Concurrent Discrete Event Systems with Linear Temporal Logic Specifications
Hierarchical Control of Concurrent Discrete Event Systems with Linear Temporal Logic Specifications
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Hierarchical Control of Concurrent Discrete Event Systems with Linear Temporal Logic Specifications

SAKAKIBARA, Ami ; USHIO, Toshimitsu

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2018/02/01, Vol.E101.A(2), pp.313-321 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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9
Expressing Algorithms as Concise as Possible via Computability Logic
Expressing Algorithms as Concise as Possible via Computability Logic
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Expressing Algorithms as Concise as Possible via Computability Logic

KWON, Keehang

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014/06/01, Vol.E97.A(6), pp.1385-1387 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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10
Optimal Control of Multi-Vehicle Systems with Temporal Logic Constraints
Optimal Control of Multi-Vehicle Systems with Temporal Logic Constraints
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Optimal Control of Multi-Vehicle Systems with Temporal Logic Constraints

KOBAYASHI, Koichi ; NAGAMI, Takuro ; HIRAISHI, Kunihiko

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2015, Vol.E98.A(2), pp.626-634 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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