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Refinado por: Nome da Publicação: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems remover
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Design space exploration for optimizing on-chip communication architectures
Design space exploration for optimizing on-chip communication architectures
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Design space exploration for optimizing on-chip communication architectures

Lahiri, K. ; Raghunathan, A. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.952-961 [Periódico revisado por pares]

New York: IEEE

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2
Software-based self-testing methodology for processor cores
Software-based self-testing methodology for processor cores
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Software-based self-testing methodology for processor cores

Li Chen ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-03, Vol.20 (3), p.369-380 [Periódico revisado por pares]

New York: IEEE

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3
System-level performance analysis for designing on-chip communication architectures
System-level performance analysis for designing on-chip communication architectures
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System-level performance analysis for designing on-chip communication architectures

Lahiri, K. ; Raghunathan, A. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-06, Vol.20 (6), p.768-783 [Periódico revisado por pares]

New York: IEEE

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4
Efficient power profiling for battery-driven embedded system design
Efficient power profiling for battery-driven embedded system design
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Efficient power profiling for battery-driven embedded system design

Lahiri, K. ; Raghunathan, A. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.919-932 [Periódico revisado por pares]

New York: IEEE

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5
Design of high-performance system-on-chips using communication architecture tuners
Design of high-performance system-on-chips using communication architecture tuners
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Design of high-performance system-on-chips using communication architecture tuners

Lahiri, K. ; Raghunathan, A. ; Lakshminarayana, G. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-05, Vol.23 (5), p.620-636 [Periódico revisado por pares]

New York: IEEE

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6
High-level crosstalk defect Simulation methodology for system-on-chip interconnects
High-level crosstalk defect Simulation methodology for system-on-chip interconnects
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High-level crosstalk defect Simulation methodology for system-on-chip interconnects

Xiaoliang Bai ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-09, Vol.23 (9), p.1355-1361 [Periódico revisado por pares]

New York: IEEE

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7
Fault-coverage analysis techniques of crosstalk in chip interconnects
Fault-coverage analysis techniques of crosstalk in chip interconnects
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Fault-coverage analysis techniques of crosstalk in chip interconnects

Yi Zhao ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-06, Vol.22 (6), p.770-782 [Periódico revisado por pares]

New York: IEEE

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8
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits
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Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits

Xiaoliang Bai ; Chandra, R. ; Dey, S. ; Srinivas, P.V.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-08, Vol.23 (8), p.1256-1263 [Periódico revisado por pares]

New York: IEEE

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9
Optimizing designs using the addition of deflection operations
Optimizing designs using the addition of deflection operations
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Optimizing designs using the addition of deflection operations

Wong, J.L. ; Potkonjak, M. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-01, Vol.23 (1), p.50-59 [Periódico revisado por pares]

New York: IEEE

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10
Resource budgeting for Multiprocess High-level synthesis
Resource budgeting for Multiprocess High-level synthesis
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Resource budgeting for Multiprocess High-level synthesis

Weidong Wang ; Raghunathan, A. ; Jha, N.K. ; Dey, S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-07, Vol.23 (7), p.1010-1019 [Periódico revisado por pares]

New York: IEEE

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