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Refinado por: assunto: Engineering remover assunto: Engineering, Electrical & Electronic remover data de publicação: 2009Até2010 remover
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Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
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Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

Guilley, Sylvain ; Sauvage, Laurent ; Flament, Florent ; Vinh-Nga Vong ; Hoogvorst, Philippe ; Pacalet, Renaud

IEEE transactions on computers, 2010-09, Vol.59 (9), p.1250-1263 [Periódico revisado por pares]

New York: IEEE

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2
Far correlation-based EMA with a precharacterized leakage model
Far correlation-based EMA with a precharacterized leakage model
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Far correlation-based EMA with a precharacterized leakage model

Meynard, Olivier ; Guilley, Sylvain ; Danger, Jean-Luc ; Sauvage, Laurent

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010, p.977-980

European Design and Automation Association

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3
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
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Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

Sauvage, Laurent ; Guilley, Sylvain ; Danger, Jean-Luc ; Mathieu, Yves ; Nassar, Maxime

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.640-645

European Design and Automation Association

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4
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Bhasin, S. ; Danger, J.-L. ; Flament, F. ; Graba, T. ; Guilley, S. ; Mathieu, Y. ; Nassar, M. ; Sauvage, L. ; Selmane, N.

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.213-218

IEEE

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5
DPL on Stratix II FPGA: What to Expect?
DPL on Stratix II FPGA: What to Expect?
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DPL on Stratix II FPGA: What to Expect?

Sauvage, L. ; Nassar, M. ; Guilley, S. ; Flament, F. ; Danger, J.-L. ; Mathieu, Y.

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.243-248

IEEE

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