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A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
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A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

Nackaerts, A. ; Ercken, M. ; Demuynck, S. ; Lauwers, A. ; Baerts, C. ; Bender, H. ; Boulaert, W. ; Collaert, N. ; Degroote, B. ; Delvaux, C. ; de Marneffe, J.F. ; Dixit, A. ; De Meyer, K. ; Hendrickx, E. ; Heylen, N. ; Jaenen, P. ; Laidler, D. ; Locorotondo, S. ; Maenhoudt, M. ; Moelants, M. ; Pollentier, I. ; Ronse, K. ; Rooyackers, R. ; Van Aelst, J. ; Vandenberghe, G. ; Vandervorst, W. ; Vandeweyer, T. ; Vanhaelemeersch, S. ; Van Hove, M. ; Van Olmen, J. ; Verhaegen, S. ; Versluijs, J. ; Vrancken, C. ; Wiaux, V. ; Jurczak, M. ; Biesemans, S.

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.269-272

IEEE

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2
A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

NACKAENS, A ; ERCKEN, M ; DE MARNEFFE, J. F ; DIXIT, A ; DE MEYER, K ; HENDRICKX, E ; HEYLEN, N ; JAENEN, P ; LAIDLER, D ; LOCOROTONDO, S ; MAENHOUDT, M ; MOELANTS, M ; DEMUYNCK, S ; POLLENTIER, I ; RONSE, K ; ROOYACKERS, R ; VAN AELST, J ; VANDENBERGHE, G ; VANDERVORST, W ; VANDEWEYER, T ; VANHAELEMEERSCH, S ; VAN HOVE, M ; VAN OLMEN, J ; LAUWERS, A ; VERHAEGEN, S ; VERSLUIJS, J ; VRANCKEN, C ; WIAUX, V ; JURCZAK, M ; BIESEMANS, S ; BAERTS, C ; BENDER, H ; BOULAERT, W ; COLLAEN, N ; DEGROOTE, B ; DELVAUX, C

Piscataway NJ: IEEE 2004

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3
Advanced process control for hyper-NA lithography based on CD-SEM measurement
Advanced process control for hyper-NA lithography based on CD-SEM measurement
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Advanced process control for hyper-NA lithography based on CD-SEM measurement

Ishimoto, T ; Sekiguchi, K ; Hasegawa, N ; Maeda, T ; Watanabe, K ; Storms, G ; Laidler, D ; Cheng, S

Proceedings of SPIE, the International Society for Optical Engineering, 2007, Vol.6518, p.65182P-65182P-11

Bellingham, Wash: SPIE

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4
Advances in process overlay
Advances in process overlay
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Advances in process overlay

HINNEN, Paul C ; MEGENS, Henry J. L ; VAN DER SCHAAR, Maurits ; VAN HAREN, Richard J. F ; MOS, Evert C ; LALBAHADOERSING, Sanjay ; BORNEBROEK, Frank ; LAIDLER, David

SPIE proceedings series, 2001, p.114-126

Bellingham WA: SPIE

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5
Advances in process overlay: ATHENA alignment system performance on critical process layers
Advances in process overlay: ATHENA alignment system performance on critical process layers
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Advances in process overlay: ATHENA alignment system performance on critical process layers

Laidler, David W ; Megens, Henry J. L ; Lalbahadoersing, Sanjay ; van Haren, Richard J. F ; Bornebroek, Frank

SPIE proceedings series, 2002, Vol.4689, p.397-408

Bellingham WA: SPIE

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6
Automatic Determination of the Number of Clusters Using Spectral Algorithms
Automatic Determination of the Number of Clusters Using Spectral Algorithms
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Automatic Determination of the Number of Clusters Using Spectral Algorithms

Sanguinetti, G. ; Laidler, J. ; Lawrence, N.D.

2005 IEEE Workshop on Machine Learning for Signal Processing, 2005, p.55-60

IEEE

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7
Characterization of overlay mark fidelity
Characterization of overlay mark fidelity
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Characterization of overlay mark fidelity

Adel, Mike ; Ghinovker, Mark ; Poplawski, Jorge M ; Kassel, Elyakim ; Izikson, Pavel ; Pollentier, Ivan K ; Leray, Philippe ; Laidler, David W

Proceedings of SPIE, 2003, Vol.5038, p.437-444

SPIE

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8
Comparison of ATHENA and TTL alignment capability in product wafers
Comparison of ATHENA and TTL alignment capability in product wafers
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Comparison of ATHENA and TTL alignment capability in product wafers

Opitz, Juliann ; Laidler, David W

SPIE proceedings series, 2002, Vol.4689, p.852-862

Bellingham WA: SPIE

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9
Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures
Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures
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Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures

Leray, Philippe ; Laidler, David W ; Pollentier, Ivan K

Proceedings of SPIE, 2003, Vol.5038, p.49-60

SPIE

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10
Effect of Ru interlayer on the crystallographic texture of AFC media
Effect of Ru interlayer on the crystallographic texture of AFC media
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Effect of Ru interlayer on the crystallographic texture of AFC media

Gonzalez-Fernandes, M.A. ; Beal, M.S. ; Laidler, H. ; Girt, E. ; Harkness, S.D.

Digest of INTERMAG 2003. International Magnetics Conference (Cat. No.03CH37401), 2003, p.DS-09

IEEE

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