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2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read
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2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Kawahara, T. ; Takemura, R. ; Miura, K. ; Hayakawa, J. ; Ikeda, S. ; Young Min Lee ; Sasaki, R. ; Goto, Y. ; Ito, K. ; Meguro, T. ; Matsukura, F. ; Takahashi, H. ; Matsuoka, H. ; Ohno, H.

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.109-120 [Periódico revisado por pares]

New York, NY: IEEE

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2
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router
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A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router

Hanzawa, S. ; Sakata, T. ; Kajigaya, K. ; Takemura, R. ; Kawahara, T.

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.853-861 [Periódico revisado por pares]

New York, NY: IEEE

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3
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
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A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Takemura, R. ; Kawahara, T. ; Miura, K. ; Yamamoto, H. ; Hayakawa, J. ; Matsuzaki, N. ; Ono, K. ; Yamanouchi, M. ; Ito, K. ; Takahashi, H. ; Ikeda, S. ; Hasegawa, H. ; Matsuoka, H. ; Ohno, H.

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.869-879 [Periódico revisado por pares]

New York, NY: IEEE

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4
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM
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Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM

Akiyama, S. ; Sekiguchi, T. ; Kajigaya, K. ; Hanzawa, S. ; Takemura, R. ; Kawahara, T.

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.107-112 [Periódico revisado por pares]

New York, NY: IEEE

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5
Spin-transfer torque RAM technology: Review and prospect : ADVANCES IN NON-VOLATILE MEMORY TECHNOLOGY
Spin-transfer torque RAM technology: Review and prospect : ADVANCES IN NON-VOLATILE MEMORY TECHNOLOGY
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Spin-transfer torque RAM technology: Review and prospect : ADVANCES IN NON-VOLATILE MEMORY TECHNOLOGY

KAWAHARA, T ; ITO, K ; TAKEMURA, R ; OHNO, H

Microelectronics and reliability, 2012, Vol.52 (4), p.613-627 [Periódico revisado por pares]

Kidlington: Elsevier

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6
Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond: Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010)
Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond: Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010)
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Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond: Special Issue Devoted to the 2nd International Memory Workshop (IMW 2010)

TAKEMURA, R ; KAWAHARA, T ; ONO, K ; MIURA, K ; MATSUOKA, H ; OHNO, H

Solid-state electronics, 2011, Vol.58 (1), p.28-33 [Periódico revisado por pares]

Kidlington: Elsevier

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7
Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers
Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers
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Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

Yiping Feng ; Takemura, G. ; Kawaguchi, S. ; Itoh, N. ; Kinget, P. R.

IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2253-2267 [Periódico revisado por pares]

New York, NY: IEEE

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