Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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11 |
Material Type: Ata de Congresso
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Layout-conscious random topologies for HPC off-chip interconnectsKoibuchi, M. ; Fujiwara, I. ; Matsutani, H. ; Casanova, H.2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA), 2013, p.484-495IEEETexto completo disponível |
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12 |
Material Type: Ata de Congresso
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L-turn routing: an adaptive routing in irregular networksKoibuchi, M. ; Funahashi, A. ; Jouraku, A. ; Amano, H.International Conference on Parallel Processing, 2001, 2001, p.383-392IEEETexto completo disponível |
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13 |
Material Type: Artigo
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A Switch-Tagged Routing Methodology for PC Clusters with VLAN EthernetKoibuchi, M ; Otsuka, T ; Kudoh, T ; Amano, HIEEE transactions on parallel and distributed systems, 2011-02, Vol.22 (2), p.217-230 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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14 |
Material Type: Ata de Congresso
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Prediction router: Yet another low latency on-chip router architectureMatsutani, H. ; Koibuchi, M. ; Amano, H. ; Yoshinaga, T.2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009, p.367-378IEEETexto completo disponível |
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15 |
Material Type: Ata de Congresso
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Descending layers routing: a deadlock-free deterministic routing using virtual channels in system area networks with irregular topologiesKoibuchi, M. ; Jouraku, A. ; Watanabe, K. ; Amano, H.2003 International Conference on Parallel Processing, 2003. Proceedings, 2003, p.527-536IEEETexto completo disponível |
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16 |
Material Type: Ata de Congresso
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VLAN-based minimal paths in PC cluster with Ethernet on mesh and torusOtsuka, T. ; Koibuchi, M. ; Jouraku, A. ; Amano, H.2005 International Conference on Parallel Processing (ICPP'05), 2005, p.567-576IEEETexto completo disponível |
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17 |
Material Type: Ata de Congresso
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Routing algorithms based on 2D turn model for irregular networksJouraku, A. ; Koibuchi, M. ; Amano, H. ; Funahashi, A.Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN'02, 2002, p.289-294IEEETexto completo disponível |
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18 |
Material Type: Artigo
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A Simple Data Transfer Technique Using Local Address for Networks-on-ChipsKoibuchi, M. ; Anjo, K. ; Yamada, Y. ; Jouraku, A. ; Amano, H.IEEE transactions on parallel and distributed systems, 2006-12, Vol.17 (12), p.1425-1437 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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19 |
Material Type: Ata de Congresso
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Balanced Dimension-Order Routing for k-ary n-cubesMontanana, J.M. ; Koibuchi, M. ; Matsutani, H. ; Amano, H.2009 International Conference on Parallel Processing Workshops, 2009, p.499-506IEEETexto completo disponível |
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20 |
Material Type: Artigo
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A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAsWANG, D. ; MATSUTANI, H. ; KOIBUCHI, M. ; AMANO, H.IEICE transactions on information and systems, 2007-12, Vol.E90-D (12), p.1914-1922 [Periódico revisado por pares]Texto completo disponível |