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Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V
Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V
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Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V

Ko, Eunah ; Lee, Jae Woo ; Shin, Changhwan

IEEE electron device letters, 2017-04, Vol.38 (4), p.418-421 [Periódico revisado por pares]

IEEE

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2
First Demonstration of a Logic-Process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications
First Demonstration of a Logic-Process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications
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First Demonstration of a Logic-Process Compatible Junctionless Ferroelectric FinFET Synapse for Neuromorphic Applications

Seo, Myungsoo ; Kang, Min-Ho ; Jeon, Seung-Bae ; Bae, Hagyoul ; Hur, Jae ; Jang, Byung Chul ; Yun, Seokjung ; Cho, Seongwoo ; Kim, Wu-Kang ; Kim, Myung-Su ; Hwang, Kyu-Man ; Hong, Seungbum ; Choi, Sung-Yool ; Choi, Yang-Kyu

IEEE electron device letters, 2018-09, Vol.39 (9), p.1445-1448 [Periódico revisado por pares]

New York: IEEE

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3
Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor
Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor
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Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

Khan, Asif Islam ; Chatterjee, Korok ; Duarte, Juan Pablo ; Zhongyuan Lu ; Sachid, Angada ; Khandelwal, Sourabh ; Ramesh, Ramamoorthy ; Chenming Hu ; Salahuddin, Sayeef

IEEE electron device letters, 2016-01, Vol.37 (1), p.111-114 [Periódico revisado por pares]

New York: IEEE

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4
High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory
High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory
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High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory

Yan, Siao-Cheng ; Lan, Guan-Min ; Sun, Chong-Jhe ; Chen, Ya-Han ; Wu, Chen-Han ; Peng, Hao-Kai ; Lin, Yu-Hsien ; Wu, Yung-Hsien ; Wu, Yung-Chun

IEEE electron device letters, 2021-09, Vol.42 (9), p.1307-1310 [Periódico revisado por pares]

New York: IEEE

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5
FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2
FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2
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FinFET With Improved Subthreshold Swing and Drain Current Using 3-nm Ferroelectric Hf0.5Zr0.5O2

Zhang, Zhaohao ; Xu, Gaobo ; Zhang, Qingzhu ; Hou, Zhaozhao ; Li, Junjie ; Kong, ZhenZhen ; Zhang, Yongkui ; Xiang, Jinjuan ; Xu, Qiuxia ; Wu, Zhenhua ; Zhu, Huilong ; Yin, Huaxiang ; Wang, Wenwu ; Ye, Tianchun

IEEE electron device letters, 2019-03, Vol.40 (3), p.367-370 [Periódico revisado por pares]

New York: IEEE

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6
Prediction of FinFET Current-Voltage and Capacitance-Voltage Curves Using Machine Learning With Autoencoder
Prediction of FinFET Current-Voltage and Capacitance-Voltage Curves Using Machine Learning With Autoencoder
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Prediction of FinFET Current-Voltage and Capacitance-Voltage Curves Using Machine Learning With Autoencoder

Mehta, Kashyap ; Wong, Hiu-Yung

IEEE electron device letters, 2021-02, Vol.42 (2), p.136-139 [Periódico revisado por pares]

New York: IEEE

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7
Enhancement-Mode Ga2O3 Vertical Transistors With Breakdown Voltage >1 kV
Enhancement-Mode Ga2O3 Vertical Transistors With Breakdown Voltage >1 kV
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Enhancement-Mode Ga2O3 Vertical Transistors With Breakdown Voltage >1 kV

Hu, Zongyang ; Nomoto, Kazuki ; Li, Wenshen ; Tanen, Nicholas ; Sasaki, Kohei ; Kuramata, Akito ; Nakamura, Tohru ; Jena, Debdeep ; Xing, Huili Grace

IEEE electron device letters, 2018-06, Vol.39 (6), p.869-872 [Periódico revisado por pares]

IEEE

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8
Self-Curable Synaptor With Tri-Node Charge- Trap FinFET for Semi-Supervised Learning
Self-Curable Synaptor With Tri-Node Charge- Trap FinFET for Semi-Supervised Learning
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Self-Curable Synaptor With Tri-Node Charge- Trap FinFET for Semi-Supervised Learning

Yu, Ji-Man ; Ham, Gyeongdo ; Kim, Seong-Yeon ; Kim, Jin-Ki ; Han, Joon-Kyu ; Yun, Seong-Yun ; Kim, Seonghak ; Lee, Sang-Won ; Jeon, Seung-Bae ; Kim, Dae-Shik ; Choi, Yang-Kyu

IEEE electron device letters, 2024-04, Vol.45 (4), p.716-719 [Periódico revisado por pares]

IEEE

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9
Demonstration of a GaN/AlGaN Superlattice-Based p-Channel FinFET With High ON-Current
Demonstration of a GaN/AlGaN Superlattice-Based p-Channel FinFET With High ON-Current
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Demonstration of a GaN/AlGaN Superlattice-Based p-Channel FinFET With High ON-Current

Raj, Aditya ; Krishna, Athith ; Hatui, Nirupam ; Gupta, Chirag ; Jang, Raina ; Keller, Stacia ; Mishra, Umesh K.

IEEE electron device letters, 2020-02, Vol.41 (2), p.220-223 [Periódico revisado por pares]

New York: IEEE

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10
Experimental Demonstration of TreeFETs Combining Stacked Nanosheets and Low Doping Interbridges by Epitaxy and Wet Etching
Experimental Demonstration of TreeFETs Combining Stacked Nanosheets and Low Doping Interbridges by Epitaxy and Wet Etching
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Experimental Demonstration of TreeFETs Combining Stacked Nanosheets and Low Doping Interbridges by Epitaxy and Wet Etching

Tu, Chien-Te ; Hsieh, Wan-Hsuan ; Huang, Bo-Wei ; Chen, Yu-Rui ; Liu, Yi-Chun ; Tsai, Chung-En ; Chueh, Shee-Jier ; Liu, C. W.

IEEE electron device letters, 2022-05, Vol.43 (5), p.682-685 [Periódico revisado por pares]

New York: IEEE

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