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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands
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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Lin, Zhiting ; Zhan, Honglan ; Li, Xuan ; Peng, Chunyu ; Lu, Wenjuan ; Wu, Xiulong ; Chen, Junning

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320 [Periódico revisado por pares]

New York: IEEE

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2
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

Jingtong Hu ; Xue, C. J. ; Qingfeng Zhuge ; Wei-Che Tseng ; Sha, E. H.

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102 [Periódico revisado por pares]

New York, NY: IEEE

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3
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory
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Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

Chen, Yuzong ; Lu, Lu ; Kim, Bongjin ; Kim, Tony Tae-Hyoung

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2636-2649 [Periódico revisado por pares]

New York: IEEE

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4
Resource-Efficient SRAM-Based Ternary Content Addressable Memory
Resource-Efficient SRAM-Based Ternary Content Addressable Memory
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Resource-Efficient SRAM-Based Ternary Content Addressable Memory

Ahmed, Ali ; Kyungbae Park ; Sanghyeon Baeg

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1583-1587 [Periódico revisado por pares]

IEEE

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5
Boosting NVDIMM Performance With a Lightweight Caching Algorithm
Boosting NVDIMM Performance With a Lightweight Caching Algorithm
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Boosting NVDIMM Performance With a Lightweight Caching Algorithm

Tsao, Che-Wei ; Chang, Yuan-Hao ; Kuo, Tei-Wei

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530 [Periódico revisado por pares]

New York: IEEE

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6
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben, John ; Pechmann, Stefan

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1108-1121 [Periódico revisado por pares]

New York: IEEE

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7
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy
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DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy

Yarmand, Roohollah ; Kamal, Mehdi ; Afzali-Kusha, Ali ; Pedram, Massoud

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.273-286 [Periódico revisado por pares]

New York: IEEE

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8
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

Putra, Rachmad Vidya Wicaksana ; Hanif, Muhammad Abdullah ; Shafique, Muhammad

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715 [Periódico revisado por pares]

New York: IEEE

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9
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
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Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Eshraghian, Kamran ; Kyoung-Rok Cho ; Kavehei, Omid ; Soon-Ku Kang ; Abbott, Derek ; Sung-Mo Steve Kang

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1407-1417 [Periódico revisado por pares]

New York, NY: IEEE

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10
Computing in Memory With Spin-Transfer Torque Magnetic RAM
Computing in Memory With Spin-Transfer Torque Magnetic RAM
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Computing in Memory With Spin-Transfer Torque Magnetic RAM

Jain, Shubham ; Ranjan, Ashish ; Roy, Kaushik ; Raghunathan, Anand

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483 [Periódico revisado por pares]

IEEE

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