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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization
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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part I: CNFET Transistor Optimization

Chen, Rongmei ; Chen, Lin ; Liang, Jie ; Cheng, Yuanqing ; Elloumi, Souhir ; Lee, Jaehyun ; Xu, Kangwei ; Georgiev, Vihar P. ; Ni, Kai ; Debacker, Peter ; Asenov, Asen ; Todri-Sanial, Aida

IEEE transactions on very large scale integration (VLSI) systems, 2022-04, Vol.30 (4), p.432-439 [Periódico revisado por pares]

New York: IEEE

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2
Impact of the Figures of Merit (FoMs) Definitions on the Variability in Nanowire TFET: NEGF Simulation Study
Impact of the Figures of Merit (FoMs) Definitions on the Variability in Nanowire TFET: NEGF Simulation Study
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Impact of the Figures of Merit (FoMs) Definitions on the Variability in Nanowire TFET: NEGF Simulation Study

Guan, Yunhe ; Georgiev, Vihar P. ; Asenov, Asen ; Liang, Feng ; Chen, Haifeng

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6394-6399 [Periódico revisado por pares]

New York: IEEE

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3
An Accurate Analytical Model for Tunnel FET Output Characteristics
An Accurate Analytical Model for Tunnel FET Output Characteristics
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An Accurate Analytical Model for Tunnel FET Output Characteristics

Guan, Yunhe ; Li, Zunchao ; Carrillo-Nunez, Hamilton ; Zhang, Yefei ; Georgiev, Vihar P. ; Asenov, Asen ; Liang, Feng

IEEE electron device letters, 2019-06, Vol.40 (6), p.1001-1004 [Periódico revisado por pares]

New York: IEEE

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4
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part II: CNT Interconnect Optimization
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part II: CNT Interconnect Optimization
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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part II: CNT Interconnect Optimization

Chen, Rongmei ; Chen, Lin ; Liang, Jie ; Cheng, Yuanqing ; Elloumi, Souhir ; Lee, Jaehyun ; Xu, Kangwei ; Georgiev, Vihar P. ; Ni, Kai ; Debacker, Peter ; Asenov, Asen ; Todri-Sanial, Aida

IEEE transactions on very large scale integration (VLSI) systems, 2022-04, Vol.30 (4), p.440-448 [Periódico revisado por pares]

New York: IEEE

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5
Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study
Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study
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Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study

Carrillo-Nunez, Hamilton ; Lee, Jaehyun ; Berrada, Salim ; Medina-Bailon, Cristina ; Adamu-Lema, Fikru ; Luisier, Mathieu ; Asenov, Asen ; Georgiev, Vihar P.

IEEE electron device letters, 2018-09, Vol.39 (9), p.1473-1476 [Periódico revisado por pares]

New York: IEEE

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6
Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices
Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices
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Multisubband Ensemble Monte Carlo Analysis of Tunneling Leakage Mechanisms in Ultrascaled FDSOI, DGSOI, and FinFET Devices

Medina-Bailon, Cristina ; Padilla, Jose L. ; Sadi, Toufik ; Sampedro, Carlos ; Godoy, Andres ; Donetti, Luca ; Georgiev, Vihar P. ; Gamiz, Francisco ; Asenov, Asen

IEEE transactions on electron devices, 2019-03, Vol.66 (3), p.1145-1152 [Periódico revisado por pares]

New York: IEEE

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7
Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects
Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects
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Atomistic- to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects

Jie Liang ; Jaehyun Lee ; Berrada, Salim ; Georgiev, Vihar P. ; Pandey, Reeturaj ; Rongmei Chen ; Asenov, Asen ; Todri-Sanial, Aida

IEEE transactions on nanotechnology, 2018-11, Vol.17 (6), p.1084-1088 [Periódico revisado por pares]

New York: IEEE

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8
Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances-Part I: Pristine MWCNT
Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances-Part I: Pristine MWCNT
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Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances-Part I: Pristine MWCNT

Chen, Rongmei ; Liang, Jie ; Lee, Jaehyun ; Georgiev, Vihar P. ; Ramos, Raphael ; Okuno, Hanako ; Kalita, Dipankar ; Cheng, Yuanqing ; Zhang, Liuyang ; Pandey, Reetu R. ; Amoroso, Salvatore ; Millar, Campbell ; Asenov, Asen ; Dijon, Jean ; Todri-Sanial, Aida

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.4955-4962 [Periódico revisado por pares]

New York: IEEE

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9
Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electrothermal Simulation Study
Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electrothermal Simulation Study
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Understanding Electromigration in Cu-CNT Composite Interconnects: A Multiscale Electrothermal Simulation Study

Lee, Jaehyun ; Berrada, Salim ; Adamu-Lema, Fikru ; Nagy, Nicole ; Georgiev, Vihar P. ; Sadi, Toufik ; Liang, Jie ; Ramos, Raphael ; Carrillo-Nunez, Hamilton ; Kalita, Dipankar ; Lilienthal, Katharina ; Wislicenus, Marcus ; Pandey, Reeturaj ; Chen, Bingan ; Teo, Kenneth B. K. ; Goncalves, Goncalo ; Okuno, Hanako ; Uhlig, Benjamin ; Todri-Sanial, Aida ; Dijon, Jean ; Asenov, Asen

IEEE transactions on electron devices, 2018-09, Vol.65 (9), p.3884-3892 [Periódico revisado por pares]

New York: IEEE

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10
Optimization and Evaluation of Variability in the Programming Window of a Flash Cell With Molecular Metal-Oxide Storage
Optimization and Evaluation of Variability in the Programming Window of a Flash Cell With Molecular Metal-Oxide Storage
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Optimization and Evaluation of Variability in the Programming Window of a Flash Cell With Molecular Metal-Oxide Storage

Georgiev, Vihar P. ; Markov, Stanislav ; Vila-Nadal, Laia ; Busche, Christoph ; Cronin, Leroy ; Asenov, Asen

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.2019-2026 [Periódico revisado por pares]

New York: IEEE

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