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Material Type: Artigo
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2018 International Symposium on Computer Architecture Influential Paper AwardGonzalez, AntonioIEEE MICRO, 2018-07, Vol.38 (4), p.76-77 [Periódico revisado por pares]Los Alamitos: IEEETexto completo disponível |
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Material Type: Ata de Congresso
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The dark side of DNN pruningYazdani Aminabadi, Reza ; Arnau Montañés, José María ; González Colás, Antonio María ; Riera Villanueva, MarcInstitute of Electrical and Electronics Engineers (IEEE) 2018Texto completo disponível |
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Material Type: Ata de Congresso
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Enabling preemptive multiprogramming on GPUsTanasic, Ivan ; Gelado, Isaac ; Cabezas, Javier ; Ramirez, Alex ; Navarro, Nacho ; Valero, Mateo2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), 2014, p.193-204IEEETexto completo disponível |
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Material Type: Ata de Congresso
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An energy-efficient and scalable eDRAM-based register file architecture for GPGPUJing, Naifeng ; Shen, Yao ; Lu, Yao ; Ganapathy, Shrikanth ; Mao, Zhigang ; Guo, Minyi ; Canal, Ramon ; Liang, XiaoyaoProceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.344-355New York, NY, USA: ACMTexto completo disponível |
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Material Type: Artigo
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A Hardware Runtime for Task-Based Programming ModelsTan, Xubin ; Bosch, Jaume ; Alvarez, Carlos ; Jimenez-Gonzalez, Daniel ; Ayguade, Eduard ; Valero, MateoIEEE transactions on parallel and distributed systems, 2019-09, Vol.30 (9), p.1932-1946 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Ata de Congresso
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A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsivenessCook, Henry ; Moreto, Miquel ; Bird, Sarah ; Dao, Khanh ; Patterson, David A. ; Asanovic, KrsteProceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.308-319New York, NY, USA: ACMTexto completo disponível |
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Material Type: Artigo
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Reducing Cache Coherence Traffic with a NUMA-Aware Runtime ApproachCaheny, Paul ; Alvarez, Lluc ; Derradji, Said ; Valero, Mateo ; Moreto, Miquel ; Casas, MarcIEEE transactions on parallel and distributed systems, 2018-05, Vol.29 (5), p.1174-1187 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Thread Assignment in Multicore/Multithreaded Processors: A Statistical ApproachRadojkovic, Petar ; Carpenter, Paul M. ; Moreto, Miquel ; Cakarevic, Vladimir ; Verdu, Javier ; Pajuelo, Alex ; Cazorla, Francisco J. ; Nemirovsky, Mario ; Valero, MateoIEEE transactions on computers, 2016-01, Vol.65 (1), p.256-269 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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Main Memory in HPC: Do We Need More or Could We Live with Less?Zivanovic, Darko ; Pavlovic, Milan ; Radulovic, Milan ; Shin, Hyunsung ; Son, Jongpil ; Mckee, Sally ; Carpenter, Paul ; Radojković, Petar ; Ayguadé, EduardACM transactions on architecture and code optimization, 2017-03, Vol.14 (1), p.1-26 [Periódico revisado por pares]ACMTexto completo disponível |
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Material Type: Artigo
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Resource-Aware Task SchedulingTillenius, Martin ; Larsson, Elisabeth ; Badia, Rosa M ; Martorell, XavierACM transactions on embedded computing systems, 2015-01, Vol.14 (1), p.1-25 [Periódico revisado por pares]ACMTexto completo disponível |