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Trading off circuit lines and gate costs in the synthesis of reversible logic
Trading off circuit lines and gate costs in the synthesis of reversible logic
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Trading off circuit lines and gate costs in the synthesis of reversible logic

Wille, Robert ; Soeken, Mathias ; Michael Miller, D. ; Drechsler, Rolf

Integration (Amsterdam), 2014-03, Vol.47 (2), p.284-294 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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2
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation
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Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation

Hubert, G. ; Artola, L. ; Regis, D.

Integration (Amsterdam), 2015-06, Vol.50, p.39-47 [Periódico revisado por pares]

Elsevier B.V

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3
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning
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An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning

Chen, Jianli ; Liu, Yan ; Zhu, Ziran ; Zhu, Wenxing

Integration (Amsterdam), 2017-06, Vol.58, p.245-252 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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4
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
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Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Foroutan, Vahid ; Taheri, MohammadReza ; Navi, Keivan ; Mazreah, Arash Azizi

Integration (Amsterdam), 2014-01, Vol.47 (1), p.48-61 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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5
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning
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An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning

Shanthi, J. ; Rani, D. Gracia Nirmala ; Rajaram, S.

Integration (Amsterdam), 2022-09, Vol.86, p.84-97 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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6
Intelligent and kernelized placement: A survey
Intelligent and kernelized placement: A survey
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Intelligent and kernelized placement: A survey

Hao, Rui ; Cai, Yici ; Zhou, Qiang

Integration (Amsterdam), 2022-09, Vol.86, p.44-50 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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7
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited)
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited)
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Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited)

Tan, Sheldon X.-D. ; Amrouch, Hussam ; Kim, Taeyoung ; Sun, Zeyu ; Cook, Chase ; Henkel, Jörg

Integration (Amsterdam), 2018-01, Vol.60, p.132-152 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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8
Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
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Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing

Bigalke, Steve ; Lienig, Jens

Integration (Amsterdam), 2020-11, Vol.75, p.189-198 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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9
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
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Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

Sun, Yang ; Cavallaro, Joseph R.

Integration (Amsterdam), 2011-09, Vol.44 (1), p.1-11 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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10
A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction
A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction
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A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction

Vidya, P. Meenakshi ; Sudha, S.

Integration (Amsterdam), 2022-03, Vol.83, p.33-45 [Periódico revisado por pares]

Amsterdam: Elsevier B.V

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