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3D source/drain doping optimization in Multi-Channel MOSFET
3D source/drain doping optimization in Multi-Channel MOSFET
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Ata de Congresso 		Adicionar ao Meu Espaço

3D source/drain doping optimization in Multi-Channel MOSFET

Tachi, K ; Vulliet, N ; Barraud, S ; Guillaumot, B ; Maffini-Alvaro, V ; Vizioz, C ; Arvet, C ; Campidelli, Y ; Gautier, P ; Hartmann, J M ; Skotnicki, T ; Cristoloveanu, S ; Iwai, H ; Faynot, O ; Ernst, T

2010 Proceedings of the European Solid State Device Research Conference, 2010, p.368-371

IEEE

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2
Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets
Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets
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Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

Barraud, S. ; Previtali, B. ; Lapras, V. ; Vizioz, C. ; Hartmann, J.-M. ; Martinie, S. ; Lacord, J. ; Casse, M. ; Dourthe, L. ; Loup, V. ; Romano, G. ; Rambal, N. ; Chalupa, Z. ; Bernier, N. ; Audoit, G. ; Jannaud, A. ; Delaye, V. ; Balan, V. ; Rozeau, O. ; Ernst, T. ; Vinet, M.

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.21.3.1-21.3.4

IEEE

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3
3D Sequential Integration: Application-driven technological achievements and guidelines
3D Sequential Integration: Application-driven technological achievements and guidelines
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3D Sequential Integration: Application-driven technological achievements and guidelines

Batude, P. ; Brunet, L. ; Fenouillet-Beranger, C. ; Andrieu, F. ; Colinge, J.-P ; Lattard, D. ; Vianello, E. ; Thuries, S. ; Billoint, O. ; Vivet, P. ; Santos, C. ; Mathieu, B. ; Sklenard, B. ; Lu, C.-M V. ; Micout, J. ; Deprat, F. ; Mercado, E. Avelar ; Ponthenier, F. ; Rambal, N. ; Samson, M.-P ; Casse, M. ; Hentz, S. ; Arcamone, J. ; Sicard, G. ; Hutin, L. ; Pasini, L. ; Ayres, A. ; Rozeau, O. ; Berthelon, R. ; Nemouchi, F. ; Rodriguez, P. ; Pin, J.-B ; Larmagnac, D. ; Duboust, A. ; Ripoche, V. ; Barraud, S. ; Allouti, N. ; Barnola, S. ; Vizioz, C. ; Hartmann, J.-M ; Kerdiles, S. ; Alba, P. Acosta ; Beaurepaire, S. ; Beugin, V. ; Fournel, F. ; Besson, P. ; Loup, V. ; Gassilloud, R. ; Martin, F. ; Garros, X. ; Mazen, F. ; Previtali, B. ; Euvrard-Colnat, C. ; Balan, V. ; Comboroure, C. ; Zussy, M. ; Mazzocchi ; Faynot, O. ; Vinet, M.

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.3.1.1-3.1.4

IEEE

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4
Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI
Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI
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Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

Bernard, E. ; Toffoli, A. ; Vidal, V. ; Delaye, V. ; Vizioz, C. ; Campidelli, Y. ; Kermarrec, O. ; Hartmann, J.M. ; Borel, S. ; Faynot, O. ; Souifi, A. ; Ernst, T. ; Coronel, P. ; Skotnicki, T. ; Deleonibus, S. ; Guillaumot, B. ; Vulliet, N. ; Garros, X. ; Maffini-Alvaro, V. ; Andrieu, F. ; Barral, V. ; Allain, F.

ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007, p.147-150

IEEE

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5
3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics
3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics
Material Type:
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3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics

Ernst, T. ; Bernard, E. ; Dupre, C. ; Hubert, A. ; Becu, S. ; Guillaumot, B. ; Rozeau, O. ; Thomas, O. ; Coronel, P. ; Hartmann, J.-M. ; Vizioz, C. ; Vulliet, N. ; Faynot, O. ; Skotnicki, T. ; Deleonibus, S.

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.265-268

IEEE

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6
Deep UV Lithography for 0.35μm Design Rules Application to CMOS Technology with Three Metallization Levels
Deep UV Lithography for 0.35μm Design Rules Application to CMOS Technology with Three Metallization Levels
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Deep UV Lithography for 0.35μm Design Rules Application to CMOS Technology with Three Metallization Levels

Vinet, F. ; Buffet, N. ; Heitzmann, M. ; Laurens, M. ; Le Cornec, C. ; Lerme, M. ; Molle, P. ; Morand, Y. ; Mourier, T. ; Ullmann, H. ; Vizioz, C.

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.299-302

IEEE

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7
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channels
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channels
Material Type:
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SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channels

MONFRAY, S ; SKOTNICKI, T ; LEVERD, F ; LE FRIEC, Y ; PANTEL, R ; HAOND, M ; CHARBUILLET, C ; VIZIOZ, C ; LOUIS, D ; BUFFET, N ; TAVEL, B ; MORAND, Y ; DESCOMBES, S ; TALBOT, A ; DUTARTRE, D ; JENNY, C ; MAZOYER, P ; PALLA, R

Piscataway NJ: IEEE 2002

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8
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels
Material Type:
Ata de Congresso 		Adicionar ao Meu Espaço

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

Monfray, S. ; Skotnicki, T. ; Tavel, B. ; Morand, Y. ; Descombes, S. ; Talbot, A. ; Dutartre, D. ; Jenny, C. ; Mazoyer, P. ; Palla, R. ; Leverd, F. ; Le Friec, Y. ; Pantel, R. ; Haond, M. ; Charbuillet, C. ; Vizioz, C. ; Louis, D. ; Buffet, N.

Digest. International Electron Devices Meeting, 2002, p.263-266

IEEE

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