Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
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1 |
Material Type: Ata de Congresso
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Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stackBernard, E. ; Ernst, T. ; Guillaumot, B. ; Vulliet, N. ; Barral, V. ; Maffini-Alvaro, V. ; Andrieu, F. ; Vizioz, C. ; Campidelli, Y. ; Gautier, P. ; Hartmann, J.M. ; Kies, R. ; Delaye, V. ; Aussenac, F. ; Poiroux, T. ; Coronel, P. ; Souifi, A. ; Skotnicki, T. ; Deleonibus, S.2008 Symposium on VLSI Technology, 2008, p.16-17IEEETexto completo disponível |
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2 |
Material Type: Ata de Congresso
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Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOIBernard, E. ; Toffoli, A. ; Vidal, V. ; Delaye, V. ; Vizioz, C. ; Campidelli, Y. ; Kermarrec, O. ; Hartmann, J.M. ; Borel, S. ; Faynot, O. ; Souifi, A. ; Ernst, T. ; Coronel, P. ; Skotnicki, T. ; Deleonibus, S. ; Guillaumot, B. ; Vulliet, N. ; Garros, X. ; Maffini-Alvaro, V. ; Andrieu, F. ; Barral, V. ; Allain, F.ESSDERC 2007 - 37th European Solid State Device Research Conference, 2007, p.147-150IEEETexto completo disponível |
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3 |
Material Type: Ata de Congresso
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3D stacked channels: how series resistances can limit 3D devices performanceBernard, E. ; Ernst, T. ; Guillaumot, B. ; Vulliet, N. ; Maffini-Alvaro, V. ; Andrieu, F. ; LeCarval, G. ; Rivallin, P. ; Vizioz, C. ; Campidelli, Y. ; Kermarrec, O. ; Hartmann, J.M. ; Borel, S. ; Delaye, V. ; Pouydebasque, A. ; Souifi, A. ; Coronel, P. ; Skotnicki, T. ; Deleonibus, S.2007 IEEE International SOI Conference, 2007, p.93-94 [Periódico revisado por pares]IEEETexto completo disponível |
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4 |
Material Type: Ata de Congresso
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3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronicsErnst, T. ; Bernard, E. ; Dupre, C. ; Hubert, A. ; Becu, S. ; Guillaumot, B. ; Rozeau, O. ; Thomas, O. ; Coronel, P. ; Hartmann, J.-M. ; Vizioz, C. ; Vulliet, N. ; Faynot, O. ; Skotnicki, T. ; Deleonibus, S.2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.265-268IEEETexto completo disponível |
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5 |
Material Type: Ata de Congresso
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Deep UV Lithography for 0.35μm Design Rules Application to CMOS Technology with Three Metallization LevelsVinet, F. ; Buffet, N. ; Heitzmann, M. ; Laurens, M. ; Le Cornec, C. ; Lerme, M. ; Molle, P. ; Morand, Y. ; Mourier, T. ; Ullmann, H. ; Vizioz, C.ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.299-302IEEETexto completo disponível |