Result Number | Material Type | Add to My Shelf Action | Record Details and Options |
---|---|---|---|
1 |
Material Type: Artigo
|
Area and power optimization approach for mixed polarity Reed–Muller logic circuits based on multi-strategy bacterial foraging algorithmZhou, Yuhao ; He, Zhenxue ; Wang, Tao ; Huo, Zhisheng ; Xiao, Limin ; Wang, XiangApplied soft computing, 2022-11, Vol.130, p.109720, Article 109720 [Periódico revisado por pares]Elsevier B.VTexto completo disponível |
|
2 |
Material Type: Artigo
|
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuitsMoaiyeri, Mohammad Hossein ; Mirzaee, Reza Faghih ; Doostaregan, Akbar ; Navi, Keivan ; Hashemipour, OmidIET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181 [Periódico revisado por pares]Stevenage: The Institution of Engineering and TechnologyTexto completo disponível |
|
3 |
Material Type: Artigo
|
On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithmShang, Qianyi ; Chen, Lijun ; Peng, PengConcurrency and computation, 2020-12, Vol.32 (23), p.n/a [Periódico revisado por pares]Hoboken: Wiley Subscription Services, IncTexto completo disponível |
|
4 |
Material Type: Artigo
|
Area and power optimization for Fixed Polarity Reed–Muller logic circuits based on Multi-strategy Multi-objective Artificial Bee Colony algorithmQin, Dongge ; He, Zhenxue ; Zhao, Xiaojun ; Liu, Jia ; Zhang, Fan ; Xiao, LiminEngineering applications of artificial intelligence, 2023-05, Vol.121, p.105906, Article 105906 [Periódico revisado por pares]Elsevier LtdTexto completo disponível |
|
5 |
Material Type: Artigo
|
A Survey of Memristive Threshold Logic CircuitsMaan, Akshay Kumar ; Jayadevi, Deepthi Anirudhan ; James, Alex PappachenIEEE transaction on neural networks and learning systems, 2017-08, Vol.28 (8), p.1734-1746United States: IEEETexto completo disponível |
|
6 |
Material Type: Artigo
|
Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits"Etiemble, DanielIEEE access, 2020, Vol.8, p.220015-220016 [Periódico revisado por pares]Piscataway: IEEETexto completo disponível |
|
7 |
Material Type: Artigo
|
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk TechnologyAgostinelli, M. ; Alioto, M. ; Esseni, D. ; Selmi, L.IEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.232-245 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
|
8 |
Material Type: Artigo
|
Synthesis of quantum-logic circuitsShende, V. V. ; Bullock, S. S. ; Markov, I. L.IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1000-1010 [Periódico revisado por pares]New York: IEEETexto completo disponível |
|
9 |
Material Type: Artigo
|
QUANTUM-DOT CELLULAR AUTOMATA-BASED SUPERIOR DESIGN OF CONSERVATIVE REVERSIBLE PARITY LOGIC CIRCUITSMajeed, Ali HJordanian journal of computers and information technology (Online), 2021-03, Vol.7 (1), p.39-50 [Periódico revisado por pares]Amman: Scientific Research Support Fund of Jordan Princess Sumaya University for TechnologyTexto completo disponível |
|
10 |
Material Type: Artigo
|
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS processMoradinezhad Maryan, Mohammad ; Azhari, Seyed Javad ; Amini-Valashani, MajidIntegration (Amsterdam), 2022-11, Vol.87, p.1-10 [Periódico revisado por pares]Elsevier B.VTexto completo disponível |