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Refinado por: assunto: Engineering remover assunto: Engineering, Electrical & Electronic remover assunto: Telecommunications remover
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1
Analysis of Electromagnetic Information Leakage From Cryptographic Devices With Different Physical Structures
Analysis of Electromagnetic Information Leakage From Cryptographic Devices With Different Physical Structures
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Analysis of Electromagnetic Information Leakage From Cryptographic Devices With Different Physical Structures

Hayashi, Y. ; Homma, N. ; Mizuki, T. ; Aoki, T. ; Sone, H. ; Sauvage, L. ; Danger, J. L.

IEEE transactions on electromagnetic compatibility, 2013-06, Vol.55 (3), p.571-580 [Periódico revisado por pares]

IEEE

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2
Efficient Evaluation of EM Radiation Associated With Information Leakage From Cryptographic Devices
Efficient Evaluation of EM Radiation Associated With Information Leakage From Cryptographic Devices
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Efficient Evaluation of EM Radiation Associated With Information Leakage From Cryptographic Devices

Hayashi, Y. ; Homma, N. ; Mizuki, T. ; Shimada, H. ; Aoki, T. ; Sone, H. ; Sauvage, L. ; Danger, J. L.

IEEE transactions on electromagnetic compatibility, 2013-06, Vol.55 (3), p.555-563 [Periódico revisado por pares]

IEEE

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3
Advanced Analysis of Faults Injected Through Conducted Intentional Electromagnetic Interferences
Advanced Analysis of Faults Injected Through Conducted Intentional Electromagnetic Interferences
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Advanced Analysis of Faults Injected Through Conducted Intentional Electromagnetic Interferences

Sauvage, L. ; Danger, J. ; Guilley, S. ; Homma, N. ; Hayashi, Y-I

IEEE transactions on electromagnetic compatibility, 2013-06, Vol.55 (3), p.589-596 [Periódico revisado por pares]

IEEE

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4
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
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Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

Sauvage, L. ; Guilley, S. ; Danger, J.-L. ; Mathieu, Y. ; Nassar, M.

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.640-645

IEEE

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5
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
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Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Bhasin, S. ; Danger, J.-L. ; Flament, F. ; Graba, T. ; Guilley, S. ; Mathieu, Y. ; Nassar, M. ; Sauvage, L. ; Selmane, N.

2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.213-218

IEEE

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6
Place-and-route impact on the security of DPL designs in FPGAs
Place-and-route impact on the security of DPL designs in FPGAs
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Place-and-route impact on the security of DPL designs in FPGAs

Guilley, S. ; Chaudhuri, S. ; Sauvage, L. ; Graba, T. ; Danger, J.-L. ; Hoogvorst, P. ; Vinh-Nga Vong ; Nassar, M.

2008 IEEE International Workshop on Hardware-Oriented Security and Trust, 2008, p.26-32

IEEE

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