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Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration.(Report)

Baranov, G. V. ; Milenin, A. P. ; Baklanov, M. P.

Russian Microelectronics, 2016, Vol.45(3), p.186(5) [Periódico revisado por pares]

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  • Título:
    Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration.(Report)
  • Autor: Baranov, G. V. ; Milenin, A. P. ; Baklanov, M. P.
  • Assuntos: Bromine Compounds ; Research Institutes
  • É parte de: Russian Microelectronics, 2016, Vol.45(3), p.186(5)
  • Descrição: To access, purchase, authenticate, or subscribe to the full-text of this article, please visit this link: http://dx.doi.org/10.1134/S1063739716030033 Byline: G. V. Baranov (1,2), A. P. Milenin (3), M. P. Baklanov (3) Abstract: The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the "fin" structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies. Author Affiliation: (1) Molecular Electronics Research Institute SC, Zelenograd, Russia (2) Moscow Institute of Physics and Technology (State University), Dolgoprudny, Russia (3) IMEC, Leuven, Belgium Article History: Registration Date: 16/05/2016 Received Date: 19/08/2015 Online Date: 19/05/2016 Article note: Original Russian Text [c] G.V. Baranov, A.P. Milenin, M.P. Baklanov, 2016, published in Mikroelektronika, 2016, Vol. 45, No. 3, pp. 197--202.
  • Idioma: Inglês

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