A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Takemura, R. ; Kawahara, T. ; Miura, K. ; Yamamoto, H. ; Hayakawa, J. ; Matsuzaki, N. ; Ono, K. ; Yamanouchi, M. ; Ito, K. ; Takahashi, H. ; Ikeda, S. ; Hasegawa, H. ; Matsuoka, H. ; Ohno, H.

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.869-879 [Periódico revisado por pares]

New York, NY: IEEE

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