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A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Munday, D. ; Parker, A. ; Anghinolfi, F. ; Aspell, P. ; Campbell, M. ; Jarron, P. ; Heijne, E.H.M. ; Meddeler, G. ; Santiard, J.C. ; Verweij, H. ; Gössling, C. ; Bonino, R. ; Clark, A.G. ; Couyoumtzelis, C. ; La Marra, D. ; Wu, X. ; Moorhead, G. ; Weidberg, A. ; Campbell, D. ; Murray, P. ; Seller, P. ; Stevens, R. ; Beuville, E. ; Rouger, M. ; Teiger, J.

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 1993-03, Vol.326 (1), p.100-111 [Periódico revisado por pares]

Elsevier B.V

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Título:
A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors
Autor: Munday, D. ; Parker, A. ; Anghinolfi, F. ; Aspell, P. ; Campbell, M. ; Jarron, P. ; Heijne, E.H.M. ; Meddeler, G. ; Santiard, J.C. ; Verweij, H. ; Gössling, C. ; Bonino, R. ; Clark, A.G. ; Couyoumtzelis, C. ; La Marra, D. ; Wu, X. ; Moorhead, G. ; Weidberg, A. ; Campbell, D. ; Murray, P. ; Seller, P. ; Stevens, R. ; Beuville, E. ; Rouger, M. ; Teiger, J.
É parte de: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 1993-03, Vol.326 (1), p.100-111
Descrição: An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.
Editor: Elsevier B.V
Idioma: Inglês

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A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Elsevier B.V

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