Idioma:

A Novel Table-Based Approach for Design of FinFET Circuits

Thakker, R.A. ; Sathe, C. ; Sachid, A.B. ; Shojaei Baghini, M. ; Ramgopal Rao, V. ; Patil, M.B.

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-07, Vol.28 (7), p.1061-1070 [Periódico revisado por pares]

New York: IEEE

Texto completo disponível

Citações Citado por

Enviar para

Título:
A Novel Table-Based Approach for Design of FinFET Circuits
Autor: Thakker, R.A. ; Sathe, C. ; Sachid, A.B. ; Shojaei Baghini, M. ; Ramgopal Rao, V. ; Patil, M.B.
Assuntos: Analog circuits ; Analytical models ; Circuit design ; Circuit simulation ; Circuits ; Computer simulation ; Design engineering ; Design optimization ; Drains ; Electric potential ; FinFET ; FinFETs ; hierarchical particle swarm optimization (PSO) ; Integrated circuit technology ; lookup table (LUT) ; Mathematical models ; MOSFETs ; Senior members ; Table lookup ; Transistor circuits ; Voltage
É parte de: IEEE transactions on computer-aided design of integrated circuits and systems, 2009-07, Vol.28 (7), p.1061-1070
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: A new lookup-table (LUT) approach, based on normalization of the drain current with an I D - V G template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.
Editor: New York: IEEE
Idioma: Inglês

Voltar para lista de resultados

Realização: Logos de Redes Sociais:

A Novel Table-Based Approach for Design of FinFET Circuits

Thakker, R.A. ; Sathe, C. ; Sachid, A.B. ; Shojaei Baghini, M. ; Ramgopal Rao, V. ; Patil, M.B.

New York: IEEE

Buscando em bases de dados remotas. Favor aguardar.