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OpenMP extensions for FPGA accelerators

Cabrera, D. ; Martorell, X. ; Gaydadjiev, G. ; Ayguade, E. ; Jimenez-Gonzalez, D.

2009 International Symposium on Systems, Architectures, Modeling, and Simulation, 2009, p.17-24

IEEE

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Título:
OpenMP extensions for FPGA accelerators
Autor: Cabrera, D. ; Martorell, X. ; Gaydadjiev, G. ; Ayguade, E. ; Jimenez-Gonzalez, D.
Assuntos: Acceleration ; Adaptive computing systems ; Application program interfaces ; Arquitectura de computadors ; Binary codes ; Blades ; Computer architecture ; Field programmable gate arrays ; Frequency estimation ; Hardware description languages ; Informàtica ; Matrix multiplication ; Message passing ; Multicore processing ; Open systems ; Parallel programming ; Programació en paral·lel (Informàtica) ; Programming profession ; Prototypes ; Research and development ; Shared memory systems ; Àrees temàtiques de la UPC
É parte de: 2009 International Symposium on Systems, Architectures, Modeling, and Simulation, 2009, p.17-24
Descrição: Reconfigurable computing is one of the paths to explore towards low-power supercomputing. However, programming these reconfigurable devices is not an easy task and still requires significant research and development efforts to make it really productive. In addition, the use of these devices as accelerators in multicore, SMPs and ccNUMA architectures adds an additional level of programming complexity in order to specify the offloading of tasks to reconfigurable devices and the interoperability with current shared-memory programming paradigms such as openMP. This paper presents extensions to openMP 3.0 that try to address this second challenge and an implementation in a prototype runtime system. With these extensions the programmer can easily express the offloading of an already existing reconfigurable binary code (bitstream) hiding all the complexities related with device configuration, bitstream loading, data arrangement and movement to the device memory. Our current prototype implementation targets the SGI Altix systems with RASC blades (based on the Virtex 4 FPGA). We analyze the overheads introduced in this implementation and propose a hybrid host/device operational mode to hide some of these overheads, significantly improving the performance of the applications. A complete evaluation of the system is done with a matrix multiplication kernel, including an estimation considering different FPGA frequencies.
Editor: IEEE
Idioma: Inglês

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OpenMP extensions for FPGA accelerators

Cabrera, D. ; Martorell, X. ; Gaydadjiev, G. ; Ayguade, E. ; Jimenez-Gonzalez, D.

IEEE

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