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Data retention under gate stress on a NVM array

Djenadi, R. ; Micolau, G. ; Postel-Pellerin, J. ; Chiquet, P. ; Laffont, R. ; Ogier, J.-L. ; Regnier, A. ; Lalande, F. ; Melkonian, J.

Solid-state electronics, 2012-12, Vol.78, p.80-86 [Periódico revisado por pares]

Kidlington: Elsevier Ltd

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Título:
Data retention under gate stress on a NVM array
Autor: Djenadi, R. ; Micolau, G. ; Postel-Pellerin, J. ; Chiquet, P. ; Laffont, R. ; Ogier, J.-L. ; Regnier, A. ; Lalande, F. ; Melkonian, J.
Assuntos: Applied sciences ; Arrays ; Data retention ; Design. Technologies. Operation analysis. Testing ; EEPROM ; Electronics ; Exact sciences and technology ; Extrinsic cells ; Gate stress ; Gating and risering ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Leakage ; Mathematical analysis ; NVM ; Oxides ; Reliability ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Stresses
É parte de: Solid-state electronics, 2012-12, Vol.78, p.80-86
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: ► We develop an original method of gate stress during data retention. ► We identify the tunnel oxide leakage path for charge losses from the floating gate. ► We extract the number of extrinsic cells in a large NVM array. This work is devoted to an original experimental method based on a classical data retention performed under a continuous gate stress. The method proposed here allows to discriminate the possible leakage paths in a non-volatile electrical memory array, but it is also the first step to the research of an equivalence between electrical stress and thermal stress. A specific array called Cell Array Structure Test (CAST) is used as a fast statistical characterization tool. The measurements are treated by a fast calculation method, allowing to extract the number of marginal cells. One of the major result of this study, apart from demonstrating the relevance of our experimental tool, lies in the demonstration and the confirmation that the charges leakage occurs mainly through tunnel oxide. This method has been applied on an EEPROM CAST – 0.09μm technology node, but it is extendable to a lot of devices and architectures.
Editor: Kidlington: Elsevier Ltd
Idioma: Inglês

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Data retention under gate stress on a NVM array

Djenadi, R. ; Micolau, G. ; Postel-Pellerin, J. ; Chiquet, P. ; Laffont, R. ; Ogier, J.-L. ; Regnier, A. ; Lalande, F. ; Melkonian, J.

Kidlington: Elsevier Ltd

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