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A 4.2-ps ECL ring-oscillator in a 285-GHz f sub(MAX) SiGe technology

Jagannathan, Basanth ; Meghelli, Mounir ; Rylyakov, Alexander V ; Groves, Robert A ; Chinthakindi, Anil K ; Schnabel, Christopher M ; Ahlgren, David A ; Freeman, Gregory G ; Stein, Kenneth J ; Subbanna, Seshadri

IEEE electron device letters, 2002-09, Vol.23 (9), p.541-543 [Periódico revisado por pares]

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Título:
A 4.2-ps ECL ring-oscillator in a 285-GHz f sub(MAX) SiGe technology
Autor: Jagannathan, Basanth ; Meghelli, Mounir ; Rylyakov, Alexander V ; Groves, Robert A ; Chinthakindi, Anil K ; Schnabel, Christopher M ; Ahlgren, David A ; Freeman, Gregory G ; Stein, Kenneth J ; Subbanna, Seshadri
Assuntos: Circuits ; Delay ; Devices ; Oscillators ; Semiconductor devices ; Silicon germanides ; Transistors ; Voltage
É parte de: IEEE electron device letters, 2002-09, Vol.23 (9), p.541-543
Notas: ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
Descrição: This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for [similar to]250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 x 2 mu m super(2) emitter size SiGe n-p-n transistors with a room temperature f sub(T) of 207 GHz and f sub(MAX) (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device.
Idioma: Inglês

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